Within the framework of progressive miniaturization of integrated circuits, trench structures are being utilized to an ever greater extent in silicon substrates for enlarging the usable surface. Trench structures for creating storage capacitors or for accepting transistors are particularly utilized in DRAM storage or memory circuits. It is important in operation that these trench structures have well-defined edges at the surface of the substrate. Defined initial structures are required at the surface of the substrate particularly for producing contacts between a storage capacitor arranged in the trench structure and a selection transistor, or for producing transistors in the trench structure.
Trench etching processes for manufacturing trench structures are known (see H. Uchida et al. Proc. of the Symp. on Dry Process J. Electrochem. Soc. Proc. Vol. 88-7, 55 (1988); M. Engelhardt Proc. 15th Annual Tegal, Plasma Seminar, 53 (1989); V. Grewal et al., 9th International Symposium on Plasma Chemistry Pugnochiuso, Italy, 1989, pp. 585-ff) wherein oxide layers are employed as an etching mask. The trench etching processes for producing trench structures having perpendicular and smooth trench walls are controlled such that passivation layers are formed at arising side walls of the trench structures during the trench etching. These passivation layers have an oxide-like composition.
The passivation layers are removed with an oxide etchant after the trench etching. The oxide etchant also attacks the etching mask. The etching mask is partially etched off and set back at the neck of the trench. The trench walls in the region of the silicon surface are therefore attacked in further etching processes, for example for deepening the trench. Since the shape of the etching mask at the trench neck was modified, a modified etching attack in the upper region of the trench ensues. The trench walls in the upper region of the trench will no longer be perpendicular in this way. This leads to problems in operation and/or performance.